////////////////////////////////////////////////////////////////////////////// 
//
//  up16_pcs_raw_macros.v
//
//  UP16-specific RAW PCS macros
//
//  Original Author: Ameer Youssef
//  Current Owner:   Ameer Youssef
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2013 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: thim $
//    $File: //dwh/up16/main/dev/pcs_raw/include/up16_pcs_raw_macros.v $
//    $DateTime: 2020/05/14 00:11:15 $
//    $Revision: #42 $
//
////////////////////////////////////////////////////////////////////////////// 

`ifdef DWC_E12MP_X4NS_RAW_PCS_MACROS_V
`else
 `define DWC_E12MP_X4NS_RAW_PCS_MACROS_V

 `include "dwc_e12mp_phy_x4_ns_macros.v"
 `include "dwc_e12mp_phy_x4_ns_pcs_raw_internal_macros.v"

 // SUP and LANE are defined in up16_cr_macros.v
 //`define DWC_E12MP_X4NS_CR_TYPE_SUP           3'b000
 //`define DWC_E12MP_X4NS_CR_TYPE_LANE          3'b001

 `define DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE      15:12
 `define DWC_E12MP_X4NS_SRAM_ADDR_LEN              12
 `define DWC_E12MP_X4NS_SRAM_ADDR_RANGE            `DWC_E12MP_X4NS_SRAM_ADDR_LEN-1:0

 // RAW_PCS TYPE mappings
 `define DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_CMN        4'b0010
 `define DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_LANE       4'b0011
 `define DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_ROM0       4'b0100
 `define DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_ROM1       4'b0101
 `define DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RAM0       4'b0110
 `define DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RAM1       4'b0111
 `define DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_LANE_BCAST 4'b1010
 
 // Use the concept of MEM lanes to increase Raw PCS memory
 // size by re-using LANE field
 `define DWC_E12MP_X4NS_CR_MEM_LANE0  4'b0000
 `define DWC_E12MP_X4NS_CR_MEM_LANE1  4'b0001
 `define DWC_E12MP_X4NS_CR_MEM_LANE2  4'b0010
 `define DWC_E12MP_X4NS_CR_MEM_LANE3  4'b0011
 `define DWC_E12MP_X4NS_CR_MEM_LANE4  4'b0100
 `define DWC_E12MP_X4NS_CR_MEM_LANE5  4'b0101
 `define DWC_E12MP_X4NS_CR_MEM_LANE6  4'b0110
 `define DWC_E12MP_X4NS_CR_MEM_LANE7  4'b0111
 `define DWC_E12MP_X4NS_CR_MEM_LANE8  4'b1000
 `define DWC_E12MP_X4NS_CR_MEM_LANE9  4'b1001
 `define DWC_E12MP_X4NS_CR_MEM_LANE10 4'b1010
 `define DWC_E12MP_X4NS_CR_MEM_LANE11 4'b1011
 `define DWC_E12MP_X4NS_CR_MEM_LANE12 4'b1100
 `define DWC_E12MP_X4NS_CR_MEM_LANE13 4'b1101
 `define DWC_E12MP_X4NS_CR_MEM_LANE14 4'b1110
 `define DWC_E12MP_X4NS_CR_MEM_LANE15 4'b1111

 // Scan chain macros (Raw CMN and Lane)
 `define DWC_E12MP_X4NS_RAW_SCAN_CR_CMN  50
 `define DWC_E12MP_X4NS_RAW_SCAN_CR_LANE 5

 // Scan chain macros (RAW x1,x2,x4)
 // (avoiding multiplication because SDB gives warning)
 `define DWC_E12MP_X4NS_RAW_X1_SCAN_CR         (`DWC_E12MP_X4NS_RAW_SCAN_CR_CMN+`DWC_E12MP_X4NS_RAW_SCAN_CR_LANE)
 `define DWC_E12MP_X4NS_RAW_X2_SCAN_CR         (`DWC_E12MP_X4NS_RAW_SCAN_CR_CMN+`DWC_E12MP_X4NS_RAW_SCAN_CR_LANE+`DWC_E12MP_X4NS_RAW_SCAN_CR_LANE)
 `define DWC_E12MP_X4NS_RAW_X4_SCAN_CR         (`DWC_E12MP_X4NS_RAW_X2_SCAN_CR+`DWC_E12MP_X4NS_RAW_SCAN_CR_LANE+`DWC_E12MP_X4NS_RAW_SCAN_CR_LANE)
 `define DWC_E12MP_X4NS_RAW_X5_SCAN_CR         (`DWC_E12MP_X4NS_RAW_X4_SCAN_CR+`DWC_E12MP_X4NS_RAW_SCAN_CR_LANE)
 `define DWC_E12MP_X4NS_RAW_X6_SCAN_CR         (`DWC_E12MP_X4NS_RAW_X4_SCAN_CR+`DWC_E12MP_X4NS_RAW_SCAN_CR_LANE+`DWC_E12MP_X4NS_RAW_SCAN_CR_LANE)

 // Scan chain macros (PHY x1,x2,x4)
 `define DWC_E12MP_X4NS_PHY_X1_SCAN_CR         (`DWC_E12MP_X4NS_PMA_X1_SCAN_CR+`DWC_E12MP_X4NS_RAW_X1_SCAN_CR)
 `define DWC_E12MP_X4NS_PHY_X2_SCAN_CR         (`DWC_E12MP_X4NS_PMA_X2_SCAN_CR+`DWC_E12MP_X4NS_RAW_X2_SCAN_CR)
 `define DWC_E12MP_X4NS_PHY_X4_SCAN_CR         (`DWC_E12MP_X4NS_PMA_X4_SCAN_CR+`DWC_E12MP_X4NS_RAW_X4_SCAN_CR)
 `define DWC_E12MP_X4NS_PHY_X5_SCAN_CR         (`DWC_E12MP_X4NS_PMA_X5_SCAN_CR+`DWC_E12MP_X4NS_RAW_X5_SCAN_CR)
 `define DWC_E12MP_X4NS_PHY_X6_SCAN_CR         (`DWC_E12MP_X4NS_PMA_X6_SCAN_CR+`DWC_E12MP_X4NS_RAW_X6_SCAN_CR)
 `define DWC_E12MP_X4NS_PHY_X1_SCAN_REF_RANGE  `DWC_E12MP_X4NS_PMA_X1_SCAN_REF_RANGE
 `define DWC_E12MP_X4NS_PHY_X2_SCAN_REF_RANGE  `DWC_E12MP_X4NS_PMA_X2_SCAN_REF_RANGE
 `define DWC_E12MP_X4NS_PHY_X4_SCAN_REF_RANGE  `DWC_E12MP_X4NS_PMA_X4_SCAN_REF_RANGE
 `define DWC_E12MP_X4NS_PHY_X5_SCAN_REF_RANGE  `DWC_E12MP_X4NS_PMA_X5_SCAN_REF_RANGE
 `define DWC_E12MP_X4NS_PHY_X6_SCAN_REF_RANGE  `DWC_E12MP_X4NS_PMA_X6_SCAN_REF_RANGE

 //FAST RX STARTUP CALIBRATION         
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_STARTUP_CAL_INIT_VAL 1'b1
 `elsif FAST_RX_STARTUP_CAL
 `define FAST_RX_STARTUP_CAL_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_STARTUP_CAL_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST RX STARTUP ADAPTATION
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_ADAPT_INIT_VAL 1'b1
 `elsif FAST_RX_ADAPT
 `define FAST_RX_ADAPT_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_ADAPT_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST RX AFE CALIBRATION         
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_AFE_CAL_INIT_VAL 1'b1
 `elsif FAST_RX_AFE_CAL
 `define FAST_RX_AFE_CAL_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_AFE_CAL_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST RX DFE CALIBRATION         
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_DFE_CAL_INIT_VAL 1'b1
 `elsif FAST_RX_DFE_CAL
 `define FAST_RX_DFE_CAL_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_DFE_CAL_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST RX BYPASS CALIBRATION         
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_BYPASS_CAL_INIT_VAL 1'b1
 `elsif FAST_RX_BYPASS_CAL
 `define FAST_RX_BYPASS_CAL_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_BYPASS_CAL_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST RX REF LEVEL CALIBRATION         
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_REFLVL_CAL_INIT_VAL 1'b1
 `elsif FAST_RX_REFLVL_CAL
 `define FAST_RX_REFLVL_CAL_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_REFLVL_CAL_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST RX IQ CALIBRATION         
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_IQ_CAL_INIT_VAL 1'b1
 `elsif FAST_RX_IQ_CAL
 `define FAST_RX_IQ_CAL_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_IQ_CAL_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on
 
 //FAST RX AFE Adaptation         
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_AFE_ADAPT_INIT_VAL 1'b1
 `elsif FAST_RX_AFE_ADAPT
 `define FAST_RX_AFE_ADAPT_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_AFE_ADAPT_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on
 
 //FAST RX DFE Adaptation         
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_DFE_ADAPT_INIT_VAL 1'b1
 `elsif FAST_RX_DFE_ADAPT
 `define FAST_RX_DFE_ADAPT_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_DFE_ADAPT_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST RX PWRUP
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_PWRUP_INIT_VAL 1'b1
 `elsif FAST_RX_PWRUP
 `define FAST_RX_PWRUP_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_PWRUP_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 //FAST SUP
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_SUP_INIT_VAL 1'b1
 `elsif FAST_SUP
 `define FAST_SUP_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_SUP_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 // PHY Functional Reset
 // synopsys translate_off
 `ifdef DWC_PHY_FUNC_RST
 `define DWC_PHY_FUNC_RST_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define DWC_PHY_FUNC_RST_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 // Firmware Override
 // synopsys translate_off
 `ifdef DWC_FW_OVRD
 `define DWC_FW_OVRD_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define DWC_FW_OVRD_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 // FAST FLAGS 2 register
 // FAST Continuous AFE calibration
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_CONT_AFE_CAL_INIT_VAL 1'b1
 `elsif FAST_RX_CONT_AFE_CAL
 `define FAST_RX_CONT_AFE_CAL_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_CONT_AFE_CAL_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 // FAST Continuous Phase calibration
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_CONT_PHASE_CAL_INIT_VAL 1'b1
 `elsif FAST_RX_CONT_PHASE_CAL
 `define FAST_RX_CONT_PHASE_CAL_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_CONT_PHASE_CAL_INIT_VAL 1'b1
 // synopsys translate_off
 `endif
 // synopsys translate_on

 // FAST Continuous Data calibration
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_CONT_DATA_CAL_INIT_VAL 1'b1
 `elsif FAST_RX_CONT_DATA_CAL
 `define FAST_RX_CONT_DATA_CAL_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_CONT_DATA_CAL_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 // FAST Continuous Adaptation
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_CONT_ADAPT_INIT_VAL 1'b1
 `elsif FAST_RX_CONT_ADAPT
 `define FAST_RX_CONT_ADAPT_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_CONT_ADAPT_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 // FAST Continuous calibration/adaptation
 // synopsys translate_off
 `ifdef ANI_SHORT_RESET
 `define FAST_RX_CONT_CAL_ADAPT_INIT_VAL 1'b1
 `elsif FAST_RX_CONT_CAL_ADAPT
 `define FAST_RX_CONT_CAL_ADAPT_INIT_VAL 1'b1
 `else
 // synopsys translate_on
 `define FAST_RX_CONT_CAL_ADAPT_INIT_VAL 1'b0
 // synopsys translate_off
 `endif
 // synopsys translate_on

 

`endif

